256k (32k x 8) static ram cy7c1399bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06490 rev. *a revised august 31, 2006 features ? temperature ranges ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? single 3.3v power supply ? ideal for low-voltage cache memory applications ? high speed: 12 ns ? low active power ? 180 mw (max.) ? low-power alpha immune 6t cell ? available in pb-free and non pb-free plastic soj and tsop i packages functional description [1] the cy7c1399bn is a high-performance 3.3v cmos static ram organized as 32,768 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ) and active low output enable (oe ) and tri-state drivers. the device has an automatic power -down feature, reducing the power consumption by more than 95% when deselected. an active low write enable signal (we ) controls the writing/reading operation of the memory. when ce and we inputs are both low, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 14 ). reading the device is accomplished by selecting the device and enabling the outputs, ce and oe active low, while we remains inactive or high. under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. the input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. the cy7c1399bn is available in 28-pin standard 300-mil-wide soj and tsop type i packages. note: 1. for guidelines on sram system design, plea se refer to the ?system design guidelines ? cypress application not e, available on t he internet at www.cypress.com. selection guide -12 -15 -20 maximum access time (ns) 12 15 20 maximum operati ng current (ma) 55 50 45 maximum cmos standby current ( a) commercial 500 500 500 commercial (l) 50 50 50 industrial 500 500 automotive-a 500 l og i c bl oc k di agram pin configurations 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view soj 12 13 25 28 27 26 gnd a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 5 i/o 0 i/o 1 i/o 2 ce oe a 0 i/o 3 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 32k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 9 a 0 a 11 a 13 a 12 a 14 a 10 [+] feedback [+] feedback
cy7c1399bn document #: 001-06490 rev. *a page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [2] .... ?0.5v to +4.6v dc voltage applied to outputs in high z state [2] ....................................?0.5v to v cc + 0.5v dc input voltage [2] .................................?0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ ........... >2001v (per mil-std-883, method 3015) latch-up current .................................................... >200 ma pin configuration 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 top view tsop 3 4 20 21 7 6 8 9 oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 0 ce i/o 7 i/o 6 i/o 5 gnd i/o 2 i/o 1 i/o 4 i/o 0 a 14 a 10 a 11 a 13 a 12 i/o 3 operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 300 mv industrial ?40 c to +85 c automotive-a ?40 c to +85 c electrical characteristics over the operating range [1] parameter description test conditions -12 -15 -20 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?2.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd v i v cc , output disabled ?5 +5 ?5 +5 ?5 +5 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 55 50 45 ma i sb1 automatic ce power-down current? ttl inputs max. v cc , ce v ih , v in v ih , or v in v il , f = f max comm?l 5 5 5 ma comm?l (l) 4 4 ma ind?l 5 5 auto-a 5 i sb2 automatic ce power-down current? cmos inputs [3] max. v cc , ce v cc ? 0.3v, v in v cc ? 0.3v, or v in 0.3v, we v cc ? 0.3v or we 0.3v, f=f max comm?l 500 500 500 a comm?l (l) 50 50 a ind?l 500 500 a auto-a 500 a notes: 2. minimum voltage is equal to ? 2.0v for pulse durations of less than 20 ns. 3. device draws low standby current regardless of switching on the addresses. [+] feedback [+] feedback
cy7c1399bn document #: 001-06490 rev. *a page 3 of 8 capacitance [4] parameter description test conditions max. unit c in : addresses input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 5 pf c in : controls 6 pf c out output capacitance 6 pf ac test loads and waveforms [5] switching characteristics over the operating range [5] parameter description -12 -15 -20 unit min. max. min. max. min. max. read cycle t rc read cycle time 12 15 20 ns t aa address to data valid 12 15 20 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 12 15 20 ns t doe oe low to data valid 5 6 7 ns t lzoe oe low to low z [6] 0 0 0 ns t hzoe oe high to high z [6, 7] 5 6 6 ns t lzce ce low to low z [6] 3 3 3 ns t hzce ce high to high z [6, 7] 6 7 7 ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 12 15 20 ns write cycle [8, 9] t wc write cycle time 12 15 20 ns t sce ce low to write end 8 10 12 ns t aw address set-up to write end 8 10 12 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 8 10 12 ns t sd data set-up to write end 7 8 10 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high z [8] 7 7 7 ns t lzwe we high to low z [6] 3 3 3 ns notes: 4. tested initially and after any design or process changes that may affect these parameters. 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and capacitance c l = 30 pf. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , t hzwe are specified with c l = 5 pf as in ac test loads. transition is measured 500 mv from steady state voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 9. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . 3.0v 3.3v output r1 317 ? r2 351 ? c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 1.73v equivalent to: thvenin equivalent all input pulses 167 ? [+] feedback [+] feedback
cy7c1399bn document #: 001-06490 rev. *a page 4 of 8 data retention characteristics (over the operating range - l version only) parameter description conditions min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 0 20 a t cdr chip deselect to data retention time 0 ns t r operation recovery time t rc ns data retention waveform 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 [11, 12] notes: 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance icc isb t hzoe t hzce t pd oe ce high v cc supply current [+] feedback [+] feedback
cy7c1399bn document #: 001-06490 rev. *a page 5 of 8 write cycle no. 1 (we controlled) [8, 13, 14] write cycle no. 2 (ce controlled) [8, 13, 14] write cycle no. 3 (we controlled, oe low) [9, 14] notes: 13. data i/o is high impedance if oe = v ih . 14. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 15. during this period, the i/os are in the out put state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 15 t wc t aw t sa t ha t hd t sd t sce we data i/o address ce data in valid data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe data in valid note 15 [+] feedback [+] feedback
cy7c1399bn document #: 001-06490 rev. *a page 6 of 8 truth table ce we oe input/output mode power h x x high z deselect/power-down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high z deselect, output disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 12 CY7C1399BN-12VC 51-85031 28-lead molded soj commercial cy7c1399bn-12vxc 28-lead molded soj (pb-free) cy7c1399bn-12zc 51-85071 28-lead tsop i cy7c1399bn-12zxc 28-lead tsop i (pb-free) cy7c1399bnl-12zc 28-lead tsop i cy7c1399bnl-12zxc 28-lead tsop i (pb-free) cy7c1399bn-12vxi 51-85031 28-lead molded soj (pb-free) industrial 15 cy7c1399bn-15vc 28-lead molded soj commercial cy7c1399bn-15vxc 28-lead molded soj (pb-free) cy7c1399bn-15zc 51-85071 28-lead tsop i cy7c1399bn-15zxc 28-lead tsop i (pb-free) cy7c1399bnl-15zxc 28-lead tsop i (pb-free) cy7c1399bnl-15vxc 51-85031 28-lead molded soj (pb-free) cy7c1399bn-15vi 28-lead molded soj industrial cy7c1399bn-15vxi 28-lead molded soj (pb-free) cy7c1399bn-15zi 51-85071 28-lead tsop i cy7c1399bn-15zxi 28-lead tsop i (pb-free) cy7c1399bn-15vxa 51-85031 28-lead molded soj (pb-free) automotive-a 20 cy7c1399bn-20zxc 51-85071 28-lead tsop i (pb-free) commercial please contact local sales representative regarding availability of these parts. [+] feedback [+] feedback
cy7c1399bn document #: 001-06490 rev. *a page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams min. max. pin 1 id 0.291 0.300 0.050 typ. 0.007 0.013 0.330 0.350 0.120 0.140 0.025 min. 0.262 0.272 0.697 0.713 0.013 0.019 0.014 0.020 0.032 0.026 a a detail external lead design option 1 option 2 1 14 15 28 0.004 seating plane note : 1. jedec std ref mo088 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.006 in (0.152 mm) per side 3. dimensions in inches 51-85031-*c 28-lead (300-mil) molded soj (51-85031) 28-lead tsop 1 (8x13.4 mm) (51-85071) 51-85071-*g [+] feedback [+] feedback
cy7c1399bn document #: 001-06490 rev. *a page 8 of 8 document history page document title: cy7c1399bn 256k (32k x 8) static ram document number: 001-06490 rev. ecn no. issue date orig. of change description of change ** 423877 see ecn nxr new data sheet *a 498575 see ecn nxr added automotive-a range removed i os parameter from dc electrical characteristics table updated ordering information table. [+] feedback [+] feedback
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